Recently, low-power circuit design is attracting a great deal of attention because of the rapidly emerging battery-powered portable electronic devices, such as notebook computers, mobile telephones, personal digital assistants (PDAs), etc. Since these portable devices are primarily in a standby mode (sometimes called a "sleep mode"), wherein they are powered but not operating, it is very important to make efforts to reduce their power consumption while in the standby mode as well as while in their various operating modes. Because semiconductor devices are frequently in the standby mode, standby mode power consumption of a semiconductor device is at least important than its operating power consumption.
Even as their operating frequencies have been increasing due to the rapid development of semiconductor fabrication technologies, there have been various attempts to lower the power consumption of semiconductor devices. Generally, in a standby mode of a semiconductor device, all components except for the input buffers (such as clock buffers and data input buffers) stop operating. Therefore, in order to reduce overall device power consumption, the power consumption of the input buffers must be taken into consideration.
FIG. 1 shows a conventional internal clock generation circuit for a synchronous semiconductor device according to the prior art. Referring to FIG. 1, the internal clock generation circuit includes a clock buffer 10 which drives a considerable amount of load. An external clock signal ECLK is simply converted into internal clock signals ICLK0-ICLKn by way of the clock buffer 10. The internal clock signals ICLK0-ICLKn are delivered to a control block 20, a data input buffer 30, a data output buffer 40, an echo clock output buffer 50, and other buffers 60, respectively. These internal buffer circuits are supplied with the internal clock signals ICLK0-ICLKn only when the external clock signal ECLK is applied to the clock buffer 10.
Unfortunately, in a synchronous semiconductor device using this internal clock generation circuit, it is impossible to operate the data input buffer 30, which is used to receive commands for switching the standby mode over to the operating mode, without the external clock signal ECLK. Therefore, the data input buffer 30 is supplied with an internal clock signal ICLK1 during the standby mode. Furthermore, the external clock signal ECLK must be supplied to the clock buffer 10 even in its standby mode. Accordingly, in this prior art internal clock generation circuit, each of the internal buffer circuits, including the data input buffer 30, is clocked during the standby mode. This presents a significant limitation on the ability to reduce power consumption in the standby mode. The industry is therefore in need of a synchronous semiconductor device having an internal clock generation circuit which operates with reduced power consumption while in a standby mode.